Traditional column redundancy schemes use either a page-buffer (SRAM) or a multiplexer. In the first scheme, a page-buffer holds data while column redundancy is being processed. In the second scheme, control logic multiplexes data from a redundancy bitline when the column counter addresses a bitline with defective memory cells. Both of these column redundancy schemes require significant chip area and processing time, especially when the implementations use high voltage devices or are located close to a memory core.
A problem with using a memory controller logic chip with serial high-density FLASH memory chips is the under-utilization of the controller logic chip functions when serial data is clocked into or out of the FLASH memory chip. During these times, while a user has control of the system clock and data, not much is concurrently occurring in the controller logic chip aside from the opening of data paths to allow data to flow to or from the user. Replacement of redundant data, if not done during this clocking period, would have to be done before the next clocking period. The resulting increases in latency and chip area required for specialized redundancy logic become more problematic as demand grows for faster serial memories with higher densities.